Conventionally, a semiconductor physical quantity sensor is known. The semiconductor physical quantity sensor is provided with multiple diffused resistors having a piezo resistance effect. The semiconductor physical quantity sensor detects an applied physical quantity based on a resistance of the diffused resistors. This kind of the semiconductor physical quantity sensor is, for example, a pressure sensor. For example, the pressure sensor has a thin portion, which is called a diaphragm. The thin portion is partially formed on a silicon substrate as a semiconductor substrate. Based on phenomena that a resistance of the diffused resistors formed on the diaphragm is changed according to pressure, the pressure sensor detects an applied pressure. Specifically, the diffused resistors provide a bridge by connecting to each other via a wiring pattern. The equilibrium state of the bridge is disturbed according to the applied pressure, so that a voltage signal is outputted according to the pressure.
In the pressure sensor having such a configuration, in order to obtain a configuration to precisely detect the pressure, an anisotropic etching is performed by an electrochemical etch-stop technique as an etching process to form the diaphragm. In the electrochemical etch-stop technique, a thickness of the diaphragm is easily controlled. When the anisotropic etching is performed with an etching solution such as a tetramethylammonium hydroxide (TMAH) solution, a predetermined voltage Vcc is applied to a portion corresponding to the diaphragm. As the etching process proceeds, when a depletion layer provided by voltage application is exposed to the etching solution, an oxide film is formed on a surface of the semiconductor substrate by anode oxidation, and therefore the etching process is stopped. Using these phenomena, the diaphragm with a predetermined thickness is formed.
Specifically, an electrical wiring is disposed to be connected in parallel to multiple chips on a wafer, and an oxide film covers a portion of a back surface of the semiconductor substrate except for a diaphragm-to-be-planned portion. Then, in the electrochemical etch-stop process, by applying the predetermined voltage Vcc to the diaphragm through the electrical wiring, the back surface of the semiconductor substrate corresponding to the diaphragm-to-be-planned portion is etched, and therefore the diaphragm is formed.
After the diaphragm is formed by such a manner, the wafer is diced along a scribe line and divided into multiple chips. In a case where the etching remainder of the electrical wiring adheres to an edge of the chip, the electrical wiring and a p-type silicon substrate may short-circuit in an operation of a semiconductor pressure sensor. To prevent a short-circuit, as shown in FIG. 10, a diode J1 is formed to provide a forward bias in voltage application in the electrochemical etch-stop process and to provide a reverse bias in the operation of the pressure sensor. Specifically, the semiconductor substrate which is formed with an n-type epitaxial layer J3 on a surface of a p-type silicon substrate J2 is used, and the diode J1 is formed. The diode J1 includes a PN junction diode on the surface portion of the n-type epitaxial layer J3. The PN junction diode includes an n+-type layer J5 and a p-type portion including a p+-type layer J4. In the electrochemical etch-stop process, the predetermined voltage Vcc, which is applied from a pad J6, is applied to an n+-type layer J10 of a diaphragm J9 through an electrical wiring J7, the diode J1, and a electrical wiring J8.
However, as shown in FIG. 10, a parasitic transistor is provided among a p-type portion of the diode J1, the n-type epitaxial layer J3, and the p-type silicon substrate J2. Therefore, in the electrochemical etch-stop process, the parasitic transistor may turn on, and current leaks from an electrical wiring to the p-type silicon substrate J2. As a result, since the current leaks to the diaphragm through the p-type silicon substrate J2, the electrochemical etch-stop process stops unexpectedly and therefore some defects may occur to result in a deficient etching treatment. Therefore, to prevent influence of the parasitic transistor, as shown in FIG. 11, conventionally an n+-type buried diffused layer J11 is added as a carrier stopper between an n layer and a p-type silicon substrate, which are disposed under a diode (referring to JP-A-H10-135484 corresponding to U.S. Pat. No. 5,932,921-A).